According to the South Korean electronics group, the first-generation 3nm process can bring down power consumption by up to 45% and decrease area by 16%, when compared to the 5nm process


Samsung Electronics announces the first ever production of 3nm process with GAA architecture. (Credit: SAMSUNG)

Samsung Electronics said that it has begun the initial production of 3-nanometer (nm) chips by using the Gate-All-Around (GAA) transistor architecture.

The South Korean electronics group deployed its Multi-Bridge-Channel FET (MBCFET) GAA technology for the first time ever for producing its 3nm process node.

Samsung Electronics claimed that the technology defies the performance limitations of fin field-effect transistor (FinFET). It enhances power efficiency by lowering the supply voltage level, while also boosting performance by increasing the capability of drive current.

The group said that it will start the first application of the nanosheet transistor with semiconductor chips for high performance, low power computing application. It has also revealed intentions to expand its application to mobile processors.

According to Samsung Electronics, the first-generation 3nm process can lower power consumption by up to 45% and decrease area by 16%, when compared to 5nm process.

The South Korean group expects the second-generation 3nm process to bring down power consumption by up to 50%, boost performance by 30%, and decrease area by 35%.

Samsung Electronics president and foundry business head Siyoung Choi said: “Samsung has grown rapidly as we continue to demonstrate leadership in applying next-generation technologies to manufacturing, such as foundry industry’s first High-K Metal Gate, FinFET, as well as EUV. We seek to continue this leadership with the world’s first 3nm process with the MBCFET.

“We will continue active innovation in competitive technology development and build processes that help expedite achieving maturity of technology.”

Samsung Electronics claimed that its proprietary technology makes use of nanosheets with broader channels. This enables increased performance and more energy efficiency when compared to GAA technologies that use nanowires with narrower channels.

By using the 3nm GAA technology, the group expects to adjust the channel width of the nanosheet for streamlining usage of power as well as performance to meet various requirements of customers.

In December 2021, the Korean group alongside IBM announced a breakthrough in semiconductor design with a new chip architecture dubbed vertical transport field effect transistors (VTFET). With this new vertical transistor architecture, Samsung Electronics believes that it is possible for scaling beyond nanosheet technology in complementary metal-oxide semiconductor (CMOS) semiconductor design.